| 摘要 |
<p>A global clock signal (CLKG) is distributed to each module (16(1)-16(N)) of a distributed synchronous logic circuit via two separate transmission lines (18A, 18B) which are of similar length but have dissimilar velocities of signal propagation. A phase difference between corresponding pulses of the global clock signal arriving at each module is proportional to the length of the transmission lines and to the inherent clock signal delay in either transmission line. A deskewing circuit (18(1)-18(N)) at each module delays the global clock signal after it arrives at the module to produce a local clock signal (CLK(1)-CLK(N)). The deskewing circuit detects the phase difference between global clock signal pulses arriving at the module to determine the inherent delay of the first transmission line and then adjusts the local clock delay so that the sum of the inherent delay and local clock delay equals a standard delay.</p> |
