A SUPERSCALAR MICROPROCESSOR INCLUDING A SELECTIVE INSTRUCTION REROUTING MECHANISM

摘要

A superscalar microprocessor is provided that includes a plurality of execution units each configured to execute the same subset of instructions. The subset of instructions may include arithmetic instructions and instructions optimized for performing DSP functionality. Instructions are routed to each of the execution units from an instruction decode unit. Each execution unit includes a plurality reservation stations for storing the instructions awaiting execution. The superscalar microprocessor advantageously includes an instruction reroute unit configured to determine whether a pending instruction within a reservation station of a particular execution unit must wait for more than a predetermined number of clock cycles before the execution unit can begin its execution. Upon detecting that a pending instruction will need to wait more than the predetermined number of clock cycles before its execution can begin, the instruction reroute unit transfers the instruction to another execution unit which is not incurring an execution bottleneck condition.