发明名称 DEETASHORISOCHINONYURYOKU*HYOJISEIGYOSOCHI
摘要 <p>PURPOSE:To provide the input and display controller of the data processor which can easily inhibit an input device from operating and also,easily erase the display of a display unit. CONSTITUTION:The controller is equipped with a signal monitor circuit 2 which is connected to an input circuit between a data processor main body 10 and input devices 11 and 12 and monitors an input signal and a signal cutoff circuit 3 which is connected to the input circuit and the display circuit of the display unit 13 and turns its circuits. Further, the controller is equipped with a timer circuit 4 which inputs the detection signal from the signal monitor circuit 2 as a reset signal and outputs a time-up signal as a cutoff signal to the signal cutoff circuit 3, a key switch 6 which controls the cutoff and connection of the signal cutoff circuit 3 according to the operation of a key, a halt switch 7 which outputs a signal to the signal cutoff circuit 3 for disconnection to halt display operation, and a halt reset switch 8 which outputs a signal to the signal cutoff circuit 3 to reset the cutoff and resets the halt of the input and display operation.</p>
申请公布号 JP2631077(B2) 申请公布日期 1997.07.16
申请号 JP19930223698 申请日期 1993.09.08
申请人 HAKAMADA YASURI SEISAKUSHO GOSHI 发明人 KOIKE MASANAO
分类号 G06F1/00;G06F1/14;G06F3/02;(IPC1-7):G06F1/00 主分类号 G06F1/00
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