| 摘要 |
<p>In a method of fabricating a semiconductor device having an N<+>-type layer or P<+>-type layer containing an impurity in a concentration of 1 x 10<19>/cm<3> or more, or a semiconductor device having a silicon based gate electrode structure containing an impurity, the final one of heat treatments each exerting an effect on the activation state of the impurity is a high rapid thermal anneal, to thereby suppress an increase in resistance of the N<+>-type layer or P<+>-type layer as a diffusion layer or improve depletion of a poly-Si based gate electrode without occurrence of variations in threshold voltage. <IMAGE></p> |
