| 摘要 |
<p>A memory line decoding driver (1) is so biased that the P channel pull-up transistor (6) biasing the final inverter (5) conducts a high current during the line address transient phase, for rapidly charging the input of the final inverter, and is turned on weakly during the static phase between one address phase and another, for reducing current consumption. For which purpose, a voltage modulating stage (18) alternatively connects the gate terminal of the pull-up transistor (6) to a capacitor (37), with which the charge is distributed, and to the supply (VPC). <IMAGE> <IMAGE></p> |
