| 摘要 |
PROBLEM TO BE SOLVED: To accelerate processing speed while effectively avoiding the acceleration of clock frequency by simultaneously and parallelly operating (n) pieces of arithmetic parts and outputting the arithmetic result outputted from these (n) pieces of arithmetic parts as the constant added result. SOLUTION: A DDA arithmetic module 10 subtracts a picture element value Cs at an arithmetic starting position from a picture element value Ce at an arithmetic ending position while using a subtraction circuit 11 and subtracts a coordinate value Xc at the arithmetic starting position from a coordinate value Xe at the arithmetic ending position while using a subtraction circuit 12. Further, a change component ΔC is calculated by dividing the subtracted result of subtraction circuit 11 with the subtracted result of subtraction circuit 12 while using a division circuit 13. A parallel constant adder circuit 15 is initialized by an initialize signal INT and operated later with a step signal ST and a clock CLK as a reference. Corresponding to the change component C and the picture element value Cs at the arithmetic starting position, the even-numbered constant added result Cpo is outputted from the picture element at the arithmetic starting position and the odd-numbered constant added result Cpe is outputted from the picture element at the arithmetic starting position simultaneously and parallelly. |
