发明名称 ALIGNMENT MARK STRUCTURE FOR SEMICONDUCTOR WAFER AND MANUFACTURE THEREOF
摘要 <p>PROBLEM TO BE SOLVED: To provide an alignment mark structure for a multilayered wiring structure which may prevent noise and provide a detection signal with high accuracy, and its manufacturing method. SOLUTION: In an alignment mark structure for a multilayered wiring structure which is formed by alternately stacking interlayer films 2, 4 and wiring layers 3, 7 on a semiconductor wafer 1, an alignment mark is formed by the interlayer film 4 patterned on a scribing line. In this alignment mark structure, the alignment mark is formed in a state where the lower wiring layer 3 on the scribing line is left.</p>
申请公布号 JPH09186221(A) 申请公布日期 1997.07.15
申请号 JP19950352717 申请日期 1995.12.28
申请人 SONY CORP 发明人 MORIKAWA TAKASHI
分类号 H01L21/68;H01L21/027;(IPC1-7):H01L21/68 主分类号 H01L21/68
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