| 摘要 |
A fabrication method of stacked DRAM(dynamic random access memory) is provided to improve properties of DRAM cells without ion-implanting process. The stacked DRAM comprises cell regions(21) and peripheral circuit regions(22) such as NMOSFET(22). The cell regions(21) includes a stacked capacitor(CA) and MOS transistor. The stacked capacitor(CA) comprises a doped polysilicon storage node(23), a dielectric layer(24) and a plate electrode(25). A gate structure(26) of the MOS transistor has triple-layers. That is, the gate structure(26) includes a bottom layer made of an insulating layer(26A), an interlayer made of silicide layer(26B), and a top layer made of undoped polysilicon layer(26C). Thereby, it is possible to simplify the process without sophisticated ion-implanting by using the gate of triple-layer structure.
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