发明名称 |
Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels |
摘要 |
A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.
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申请公布号 |
US5646897(A) |
申请公布日期 |
1997.07.08 |
申请号 |
US19950426384 |
申请日期 |
1995.04.21 |
申请人 |
HITACHI, LTD. |
发明人 |
YUKUTAKE, SEIGOU;IWAMURA, MASAHIRO;MITSUMOTO, KINYA;AKIOKA, TAKASHI;AKIYAMA, NOBORU |
分类号 |
G11C7/10;G11C29/34;G11C29/50;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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