发明名称 Method and apparatus for reducing rounding error when evaluating binary floating point polynomials
摘要 Rounding error can be reduced when evaluating binary floating point polynomials utilizing a Floating Point Unit (58) by first computing the sum of products of second and higher order polynomial terms. Next, the Floating Point Unit (58) adds a zeroth level term to the product of a first order coefficient and an independent variable to form a "Big" term. The Floating Point Unit (58) calculates as a "Little" term the rounding error resulting from the computation of the "Big" term. The "Little" term is then added to the sum of products of higher order terms to form an "Intermediate" term. Finally, the Floating Point Unit (58) adds the "Big" term to the "Intermediate" term to form the polynomial result corrected by the rounding error introduced by the computation of the low order terms.
申请公布号 US5646876(A) 申请公布日期 1997.07.08
申请号 US19950424032 申请日期 1995.04.18
申请人 MOTOROLA, INC. 发明人 SMITH, ROGER A.
分类号 G06F7/552;(IPC1-7):G06F7/38 主分类号 G06F7/552
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