发明名称 |
Dynamic phase selector phase locked loop circuit |
摘要 |
A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.
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申请公布号 |
US5646968(A) |
申请公布日期 |
1997.07.08 |
申请号 |
US19950560013 |
申请日期 |
1995.11.17 |
申请人 |
ANALOG DEVICES, INC. |
发明人 |
KOVACS, JANOS;KROESEN, RONALD;MCCALL, KEVIN |
分类号 |
H03K3/0231;H03K3/03;H03L7/081;H03L7/087;H03L7/099;H03L7/14;(IPC1-7):H03D3/24 |
主分类号 |
H03K3/0231 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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