In a redundant memory device, the redundant memory device is provided which is characterized in that the supply of a driving pulse to a comparison and selection means which generates an activating pulse of a reserve row/column in response to the result of comparison of the address of a defective memory cell and an input address code can be programmed so as to be inhibited for a surplus comparison and selection means during the inspection process. By this arrangement, the power consumption in the comparison and selection means can be reduced, and high level of integration of the memory chip can be facilitated accordingly. <IMAGE>
申请公布号
DE69219951(D1)
申请公布日期
1997.07.03
申请号
DE1992619951
申请日期
1992.06.25
申请人
NEC CORP., TOKIO/TOKYO, JP
发明人
TSUJIMOTO, AKIRA, C/O NEC CORPORATION, MINATO-KU, TOKYO, JP