SILICON BIPOLAR JUNCTION TRANSISTOR HAVING REDUCED EMITTER LINE WIDTH

摘要

The present invention is drawn to a silicon bipolar junction transistor having emitter line spacings on the order of approximately 0.25 microns or less. The present invention utilizes a conventional structure for a bipolar junction transistor. A layer of silicon dioxide (201) is grown and selectively etched after photolithography, masking and etching techniques in the desired regions for the emitter, collector and base. A layer of silicon nitride (203) is disposed on the layer of silicon dioxide, having been deposited over the entire surface of the wafer containing the etched 0.5 micron width line features at the emitter base and collector sites. Low pressure chemical vapor deposition (LPCVD) enables uniform silicon nitride growth both vertically from the surface and horizontally from the feature sidewalls. The deposited film of silicon nitride is then etched using standard reactive ion etching (RIE) techniques, removing the silicon nitride from horizontal surfaces without removing the silicon nitride from the side walls of the etched patterns. The resultant spacer (400) of silicon nitride is attached to the side wall of the original feature, thereby reducing the window of the original features by a dimension approximately two times the thickness of the deposited silicon nitride.