The delay circuit includes a fixed-delay circuit (D1) supplying a signal (e1) with is delayed with respect to the input signal (e0). It comprises a combinatorial circuit (C) which supplies a combinatorial signal (fK) resulting from the weighted superposition with integral effect of the input (e0) and delayed (e1) signals. The whole unit is designed such that the fixed delay (T) is less than the transition time exhibited by the combinatorial signal (fK) when only the input signal (e0) is applied. Devices produced in ECL and CMOS technologies. Application in particular to phase-locked circuits. <IMAGE>
