发明名称 A dual damascene process
摘要 A dual damascene process forms a two level metal interconnect structure by first providing a interlayer oxide 52 over a device structure 50 and covering the interlevel oxide layer with an etch stop layer 54. The etch stop layer is patterned to form tapered openings 72 corresponding to the pattern of the interconnects that are to be formed in the first level of the two level interconnect structure. After the etch stop layer is patterned, an intermetal oxide layer 56 is provided over the etch stop layer. Because the etch stop layer is relatively thin, the topography formed on the surface of the intermetal oxide layer is relatively small. A photoresist mask is then provided over the intermetal oxide layer with openings in the mask exposing portions of the intermetal oxide layer in the pattern of the wiring lines to be provided in the second level of the interconnect structure. The intermetal oxide layer is etched and the etching process continues to form openings in the interlayer oxide where the interlayer oxide is exposed by the openings in the etch stop layer. Thus, in a single etching step, the openings for both the second level wiring lines and the first level interconnects are defined. Metal is then deposited over the structure and excess metal is removed by chemical mechanical polishing to define the two level interconnect structure.
申请公布号 GB9709431(D0) 申请公布日期 1997.07.02
申请号 GB19970009431 申请日期 1997.05.09
申请人 UNITED MICROELECTRONICS CORPORATION 发明人
分类号 H01L21/28;H01L21/3205;H01L21/768;H01L23/522 主分类号 H01L21/28
代理机构 代理人
主权项
地址