| 摘要 |
A MOS ROM architecture which is fast-switching, requires almost no current under static conditions and only small current while switching, does not require a precharge mechanism and exhibits high immunity to electrical noise. A flash converter using this ROM architecture has a "one of" circuit driving a ROM encoder stage. The ROM constitutes a "one-of" to Gray- or modified Gray code encoder, or a "one-of" to binary encoder. Each bit cell in the ROM has a single NMOS transistor with its drain connected to either zero volts (representing logical 0) or to a VDD supply of, for example, 5 volts (representing logical 1). The transistor's source is connected to the bit line. All bit cell transistor gates for a given ROM address (i.e., location) are driven in parallel by an enable/disable signal. Preferably, the N-channel transistors whose drains are connected to logical 0 are about twice as large as those whose drains are connected to logical 1, to achieve desirable drain-to-source "on" resistance, Ron, and obtain a "low" output voltage when sparkle codes occur. Each bit line is connected to a buffer inverter whose trigger point is scaled to operate with a bit line that can only swing as high as VDD-VT (i.e., one threshold voltage below the supply voltage, VDD) when the bit line is connected to a logical 1. There is high noise immunity because the bit lines are always driven and do not float at high impedance. Static current is drawn only when there is a thermometer code bubble, causing bit cell transistors to contend for control of a bit line. Otherwise, current is needed only during switching.
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