发明名称 |
Dynamically partitionable digital video encoder processor |
摘要 |
Disclosed is a digital video encoder processor for discrete cosine transform encoding. The discrete cosine transform encoding includes the encoding steps of (1) determining the discrete cosine transform field or frame type, (2) addressing individual pixels as either (i) vertically adjacent pixels on consecutive Odd and Even field lines, or (ii) vertically adjacent pixels on consecutive Odd field lines, then consecutive Even field lines; or (iii) vertically adjacent pixels on consecutive Even field lines, then consecutive Odd field lines. These subtractions may be performed between (i) consecutive lines, (ii) odd lines, or (iii) even lines. The next step is finding the smallest variance of the above subtractions to determine the discrete cosine transform coding type. The subtractions are carried out in a dynamically partitionable processor having a plurality of datapaths. The datapaths are partitionable by the action of running opcode into (i) a single wide datapath, and (ii) a plurality of narrow datapaths for calculating the absolute value of the difference between two pixels, and accumulating the results of the subtraction.
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申请公布号 |
US5644504(A) |
申请公布日期 |
1997.07.01 |
申请号 |
US19950411239 |
申请日期 |
1995.03.27 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BOICE, CHARLES EDWARD;KACZMARCZYK, JOHN MARK;NGAI, AGNES YEE;WOODARD, ROBERT LESLIE |
分类号 |
G06T9/00;H04N7/26;H04N7/30;(IPC1-7):G06K15/00 |
主分类号 |
G06T9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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