| 摘要 |
A universal sequential logic circuit is constructed from a rectilinear array of elementary logic "cells", with a relatively large number of logic states embodied in a relatively small array. The set of states from a state-machine description of the logic function desired to be performed is compiled into a software association of cellular array states with each state-machine state (4), and the set of transitions from the state-machine description is compiled into a software association of logical connections between cells. The cellular array performs the state-machine function under software control. The rectilinear array (1a) generally embodies one bit of cellular array state information for each row of logic cells, stored in diagonal cells of the array called "memory cells" (2). Non-diagonal cells of the array called "function cells" (3) are controlled by stored software, which controls the transfer of cellular array state information from each row to each other. Equivalence classes of state-machine states with respect to sequences of inputs are compiled, and one memory cell state is assigned to each such equivalence class. The function cells select which cellular array state follows the present one by selecting which logic state each memory cell in the array is to store next, each using a multiplexor under the control of stored memory bits.
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