发明名称 CLOCK GENERATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To generate a stable clock in spite of a period when reference time information is given. SOLUTION: A period counter 2 counts the period when reference time information is given. A time counter 1 presets the value of 'reference time information +1" and counts up time with a self generation clock. When reference time information is given, the value and the value of the time counter are subtracted in a subtracter 4. The subtracted result is divided by the value of the period counter 2. The divided result is converted into an analog signal by a D/A converter 7 and the oscillation frequency of VCO(voltage control oscillator) 9 is controlled. Since the division of the subtracted result of the subtracter 4 by the value of the period counter 2 is equivalent to the deviation of reference time information and the oscillation frequency of VCO 9, VCO 9 can stably be controlled in spite of the period when reference time information is given.
申请公布号 JPH09172373(A) 申请公布日期 1997.06.30
申请号 JP19950330947 申请日期 1995.12.20
申请人 NEC CORP 发明人 IIJIMA TAKAYUKI
分类号 H03L7/181;H04N5/06;H04N7/24;H04N19/00;H04N19/70;H04N19/80;H04N19/85 主分类号 H03L7/181
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