| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a data output control circuit of a hyper page mode capable of control with write enable signals as well. SOLUTION: A precharge control signal generation circuit 3 generates precharge control signals PDOP in response to signals RASB and CASB and addresses, a precharge signal generation circuit 5 generates precharge signals CLKP in response to the signals PDOP and output enable control signals POWE and a precharge circuit 7 precharges data bus lines DB/DBB corresponding to the signals CLKP. An output enable control signal generation circuit 120 outputs the signals POWE from output enable signals OEB, the signals CASB and the write enable signals WEB, a write enable latch signal generation circuit 130 latches the signals WEB corresponding to the signals CASB and generates latch signals PEWDC-L and a trigger signal generation circuit 9 generates trigger signals CLKT corresponding to the signals CASB, RASB, the addresses and the signals PEWDC-L. An output buffer and driver 11 decides the data output state according to the data bus lines corresponding to the trigger signals CLKT.</p> |
