| 摘要 |
PROBLEM TO BE SOLVED: To reduce to an area of memory cells by a method wherein first and second word lines are symmetrically arranged, a lead-out line is connected to one output node, the other lead-out line is connected to a bit line and the lead-out line is led out in a Y direction from the output node in the same direction. SOLUTION: A second memory cell 12 adjacent to a first memory cell 11 in an X direction, word lines, etc., are symmetrically arranged with respect to a Y axis. A contact area 14a of the first bit line is arranged on a second word line 7, a contact area 14b of a second bit line on a fourth word line 9, a contact area 14c of a third bit line on a third word line 8, and a contact area 14d of a fourth bit line on a first word line 6. A lead-out line is connected to a bit line and an output node 30. The bit line contact area, a bit line through hole 15, a lead-out line 18 and a contact 19 are a layout asymmetrical to a Y axis, and it is possible to reduce an area by leading out in a Y direction in the same direction. |
