DELAY CIRCUIT AND DIGITAL PHASE LOCK CIRCUIT

摘要

PROBLEM TO BE SOLVED: To realize different delay times for the delay circuit by adopting a variable capacitor for a capacitor connected between a 1st inverting buffer and a 2nd inverting buffer. SOLUTION: A 1st inverting buffer is made up of a 1st P-channel field effect transistor 4 and a 1st N-channel field effect transistor 5 and a 2nd inverting buffer is made up of a 2nd P-channel field effect transistor 4a and a 2nd N- channel field effect transistor 5a. Furthermore, capacitors being P-channel field effect transistors 4b-4d are connected in parallel with capacitors being N-channel field effect transistors 5b-5d respectively. Then 1st-3rd transmission gates 6, 6a, 6b act like switches. Thus, the delay circuit is realized, in which its delay time is made variable by the selection of a transmission gate to be switched on.