| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the number of timer registers to only one and to reduce the whole circuit scale by providing plural matching data storage circuits storing the timer values corresponding to each counter without providing a register block with a matching detection function and transferring the timer value of the matching data storage circuit selected in response to the supply of an operating control signal to the timer register. SOLUTION: This circuit is provided with a register block 3A including a buffer circuit 30 in place of a register block, four counters 31A to 31D, a timer register 32 which is the same as a timer register 32A, a bus connection circuit 34 and four matching data storage circuits 33A to 33D, a matching flag 4A holding the matching detection of the timer register 32 and a transfer control circuit outputting each of the selection signals CSA to CSD of the matching data storage circuit in response to the supplies of capture trigger/timer selection signals TSA to TSD, in addition to an incrementer 1, a latch circuit 2, a clear control part 5, an operating control part 6 and an internal bus 9, which are common to a conventional circuit.</p> |
