TIMING SIGNAL GENERATOR

摘要

A timing signal generator (10) includes a voltage controlled oscillator (VCO) (14), a logic circuit (21), N set circuits (19), N reset circuits (20) and a bistable latch circuit (23). The VCO produces a set of N reference signals (T1-TN) frequency locked to a reference clock signal (T1) and distributed in phase so as to evenly resolve the reference clock period into N intervals. The logic circuit (21) asserts ones of N set signals (SE1-SEN) and N reset signals (RE1-REN) selected by input control words. The timing of leading and trailing edges of pulses of the output timing signal (26) may be controlled with a resolution that is 1/Nth of the period of the reference clock by supplying an appropriate control word sequence to the logic circuit.