| 摘要 |
A dual processor computer system with error checking that stops immediately when a discrepancy is detected between the two processors. The system includes a first processing system (20) for executing a series of instructions including input/output instructions. A second processor (30) executes the same instructions independently of and in synchronization with the first processing system. All significant processor address, data, and control signals are connected to all peripheral devices by a processor independent I/O bus (10). A comparison circuit (9) which detects discrepancies in the operation of the two lock step processing systems is connected between the processors and the processor independent I/O bus. The comparison circuit provides a signal that immediately stops operation of the processors when an error is detected. The I/O bus is independent of the processor type, clock rate, and peripherals chosen in the construction of the computing system. This independence allows the computing system to be upgraded with faster processors and newer peripherals, without having to redesign the computing platform and the error checking circuit. |
