Synchronous semiconductor memory apparatus, e.g. synchronous DRAM

摘要

The apparatus, which works synchronously with an externally applied clock signal (CLK), includes an output buffer circuit (6), a mask signal production circuit (16) which produces an output mask instruction signal (QM), and an output control circuit (30). The output buffer is connected to a data output connection (DQ) to which it applies a loaded value when activated by a signal (OEM) from the control circuit. Also provided is a read-free signal production circuit (24) which receives address and write enable signals via a control buffer circuit (8) and a read instruction decoder (10) to produce a data-free signal (OEMF). The data-free signal instructs a data read operation in response to an externally applied data read instruction signal. The output mask instruction signal (QM), which deactivates the output buffer, is output in response to the activation of an externally applied read-free data mask instruction signal (extDQM). The control circuit receives both the instruction signals and includes a delay circuit (30a,30b) which delays the data-free signal for a predetermined number of clock cycles and a gate circuit (30c,30d) which receives both the delayed read-free signal and the mask signal to output a signal (B) to a further delay circuit (30e). An AND gate (30f) receives the outputs from the latter delay circuit (OEMQM) and the read-free signal circuit (OEMF) to output the buffer activation signal (OEM).