Operation mode setting circuit apparatus for semiconductor DRAM

摘要

The apparatus includes a correspondence setting circuit (10) and a mode-determining-signal generator circuit (20). Provided with the holding circuit is a locking circuit (12), e.g. an inverter, and a non-locking circuit (14), e.g. a buffer, both connected to a selection circuit (16), e.g. a CMOS transfer gate. Both the inverter and the transfer gate are in receipt of one mode change signal (MCHG) and the buffer is in receipt of a second mode change signal (ZMCHG). The setting circuit changes the correspondence between the state of externally supplied signals (EXT) and the state of internal signals (INT) according to an operation mode change signal (MCHG). These internal signals are then supplied to the mode determination circuit from the setting circuit. The mode determination circuit then supplies a mode signal (MODE) to an internal circuit according to the state of the signal (INT) from the setting circuit.