发明名称 |
A NEGATIVE VOLTAGE SWITCH ARCHITECTURE FOR A NONVOLATILE MEMORY |
摘要 |
A negative voltage switching circuit in a nonvolatile memory includes a switching transistor (94) coupled to an output of the negative voltage switching circuit and a first voltage source that has a voltage level substantially lower than zero volts. A pull-up circuit (141, 143, 144) is coupled to a control terminal of the switching transistor (94) and selectively to a second voltage source having a voltage level substantially above zero volts. The pull-up circuit (141, 143, 144) applies the second voltage source to the control terminal of the switching transistor (94) when the pull-up circuit (141, 143, 144) is coupled to the second voltage source such that the switching transistor (94) does not couple the first voltage source to the output. A pull-down circuit (142, 147) is coupled to the first voltage source and the control terminal of the switching transistor (94). The pull-down circuit (142, 147) applies the first voltage source to the control terminal of the switching transistor (94) when the pull-up circuit (141, 143, 144) is not coupled to the second voltage source such that the switching transistor (94) couples the first voltage source to the output.
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申请公布号 |
WO9722971(A1) |
申请公布日期 |
1997.06.26 |
申请号 |
WO1996US19687 |
申请日期 |
1996.12.12 |
申请人 |
INTEL CORPORATION;JAVANIFARD, JAHANSHIR, J.;EVERTT, JEFFREY, J. |
发明人 |
JAVANIFARD, JAHANSHIR, J.;EVERTT, JEFFREY, J. |
分类号 |
G11C16/16;G11C16/30;(IPC1-7):G11C7/00 |
主分类号 |
G11C16/16 |
代理机构 |
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主权项 |
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地址 |
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