Complementary clock pulse generator with inverter unit

摘要

The inverter unit (10) transmits voltage levels Vcc-Vtn and Vss+Vtp by increasing and reducing voltage and earthing voltage according to a clock pulse signal applied externally. A first buffer (20) transmits the above mentioned voltages. A level converter (30) receives the inverter unit and buffer voltages and restores them to a signal with a CMOS level. Two further buffers (40,50) invert the output of the level converter and transmit a normal and an inverted clock pulse signal.