| 摘要 |
<p>An asynchronous bridge (100, 120) is provided to allow interoperability between devices (102, 104) operating at different clock frequencies. A first command message from the first device (102, 104) is received and stored in a bridge (100, 120). The first command message is transmitted to the second device (104, 102) and a reply message responsive to the first command message is received in the bridge (100, 120) and transmitted to the first device (102, 104). This asynchronous bridge is useful in the development of bus components and expansion boards and provides an interface between devices operating at independent or independently controllable clock speeds. <IMAGE></p> |
