| 摘要 |
A data sampling circuit and method is provided for a burst mode communication system. The circuit is an entirely digital circuit for reliably sampling an incoming stream of data for automatically adjusting to variations in data stream clock rates and phase variations in the incoming data. The circuit includes a delay line, with a plurality of serially coupled taps, each tap having a variable delay. A first aspect of the invention includes increasing the delay time until the delay line captures at least one full data cell, but preferably two, of the incoming data stream (i.e., signal levels over at least one full clock period, defined by two transitions of the data stream), thereby aligning the receiving circuit with the frequency of the data stream clock. A second aspect of the invention includes outputting data from a tap that is selected to be midway between two regions of transitions of the incoming data stream, thereby aligning the receiving circuit with the phase of the data stream clock. The invention can, in alternative embodiments, track changes in the input data stream's phase/frequency. This involves updating the amount of delay in each tap of the delay line as well as picking the output of the appropriate tap to be used as the sampled data stream, in response to changes in the input signal as well as changes in propagation delays, of the circuits used to implement the delay line, resulting from temperature and voltage variations.
|
