发明名称 VIDEO CLOCK GENERATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To generate clock signals with plural frequencies by one oscillator and a digital circuit. SOLUTION: The generating circuit is provided with an oscillator 10 generating a basic clock, a delay signal generating means 1 delaying sequentially a basic clock oscillated from the oscillator 10 and providing an output of n-sets of delay signals synchronously with the basic clock, and a differentiation signal generating circuit 14 generating n-sets of differentiation signals based on two adjacent signals each in the n-sets of delay signals outputted from the delay signal generating means 1. Then the delay signal generating means 1 is provided with a video clock generating means 2 selecting the differentiation signals of a number based on the setting of the predetermined video clock and generating the video block based on the selected differentiation signals.
申请公布号 JPH09168085(A) 申请公布日期 1997.06.24
申请号 JP19950328844 申请日期 1995.12.18
申请人 NEC CORP 发明人 AKIYAMA MINORU
分类号 G02B26/10;G03G15/04;G03G15/043;H04N1/387;H04N5/76;(IPC1-7):H04N1/387 主分类号 G02B26/10
代理机构 代理人
主权项
地址
您可能感兴趣的专利