| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide an address decoding circuit for synchronous semiconductor memory capable of speeding up the decoding speed. SOLUTION: This circuit has a read address decoder 100 and a write address decoder 120 having constitution in which at the time of differentiating between a read address and a write address from addresses to be inputted to an address buffer 2, enable signals KPASSREAD, KPASSWRITE for differentiate the read address between the write address are impressed on addresses after the decoding of the input addresses. The the delay time required for the decoding is made to be shortened by making the circuit the constitution in which the enable signals discriminating between the read address and the write address are impressed on the addresses after decoding of the input address.</p> |
