| 摘要 |
PROBLEM TO BE SOLVED: To reduce the time required for locking by setting a dot clock frequency while taking into account the temperature characteristic of a PLL(phase- locked loop) circuit, and reducing the number of data through reduction in the overlap lead-in ranges. SOLUTION: A display circuit part 7 is used to determine the frequency of a horizontal synchronizing signal from a terminal 1, and data is transmitted to a CPU 10, which accordingly performs switching of the display circuit part 7, etc., and at the same time, controls a clock generator 5. The clock generator 5 converts signal from a VCO(voltage-controlled transmitter) 4 into a required frequency for output, that is based on the determination of the horizontal frequency. A temperature detecting part 9 is used to detect the temperature inside the device, and from a storage part 8, the CPU 10 reads a data table corresponding to the temperature inside the device from those set for the horizontal frequency, and transmits it to the clock generator 5. The display circuit part 7 determines whether a PLL is locked or unlocked, and the clock generator 5 is controlled via the CPU 10 so that the retraction range of the PLL is attained. |
