发明名称 |
BURST SYNCHRONIZATION CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To receive correctly data for each of burst data reception. SOLUTION: The burst synchronization circuit provided with a sampling means 1, an edge detection means 2, and a data selection means 3 is provided with an optimum phase selection means 4 which ORs edges of plural detected burst data from the edge detection means 2 conducting plural number of times of edge detection to plural burst data and provides a phase selection signal to select a phase corresponding to a center of a longest interval among adjacent edge intervals as the result of OR to the selection means 3. |
申请公布号 |
JPH09162853(A) |
申请公布日期 |
1997.06.20 |
申请号 |
JP19950324442 |
申请日期 |
1995.12.13 |
申请人 |
FUJITSU LTD;NIPPON TELEGR & TELEPH CORP <NTT> |
发明人 |
SHINOMIYA TOMOHIRO;HIROTA MASAKI;KAWAI MASAAKI;TAJIMA KAZUYUKI;ABIRU SETSUO;MIYABE MASATAKE;MAEKAWA EIJI |
分类号 |
H03K5/00;H04L7/02;H04L7/027 |
主分类号 |
H03K5/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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