发明名称 ERROR DETECTOR OF SYSTEM TIME CLOCK
摘要 PROBLEM TO BE SOLVED: To synchronize the STC of a decoder with the PCR of an encoder by finding an error by comparing the PCR with the STC in an MPEG system. SOLUTION: An error generating part 1 receives the count values of program clock reference value (PCR-BASE, EXT) and system time clock (STC-BASE, EXT) and outputs the error value of STC. This output is inputted through a loop filter 2 to a VCO 3. The output of VCO 3 is connected to a frequency divider 4, and the output signal of the frequency divider 4 is connected to the CK terminal of the 1st counter 5 and the RESET terminal of the 2nd counter 6. The count value of STC-BASE is outputted from the 1st counter 5 to the error generating part 1, and the count value of STC-EXT is outputted from the 2nd counter 6 to the error generating part 1.
申请公布号 JPH09163364(A) 申请公布日期 1997.06.20
申请号 JP19960276648 申请日期 1996.10.18
申请人 SAMSUNG ELECTRON CO LTD 发明人 BUN HEIJIYUN
分类号 H04N19/102;H03L7/181;H04N7/24;H04N7/62;H04N19/00;H04N19/134;H04N19/196;H04N19/70;H04N19/82 主分类号 H04N19/102
代理机构 代理人
主权项
地址