发明名称 DATA RECEIVER
摘要 PROBLEM TO BE SOLVED: To provide the data receiver in which information obtained from functions in existence in conventional receivers is utilized so as to detect a fast speed additional control channel (FACCH) with high accuracy almost without increasing an arithmetic quantity. SOLUTION: A flag (information bit) representing a fast speed additional control channel (FACCH) in a decoding frame unit is detected from a signal with a likelihood added thereto by a likelihood addition section 53. When the content of the flag (information bit) detected by a flag detection section 54 indicates the fast speed additional control channel (FACCH), a FACCH discrimination section 56 adds the likelihood corresponding to the flag (information bit) to the signal. Furthermore, when the content of the detected flag (information bit) does not indicate the fast speed additional control channel (FACCH), the FACCH discrimination section 56 subtracts the likelihood corresponding to the flag (information bit) from the signal. When the result is larger than a threshold level stored in a memory 55, the channel is discriminated to be the fast speed additional control channel (FACCH) and when smaller, the channel is discriminated to be other channel.
申请公布号 JPH09162800(A) 申请公布日期 1997.06.20
申请号 JP19950346323 申请日期 1995.12.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SAITO YOSHIKO;UESUGI MITSURU
分类号 H04B7/26;H04B17/00;H04Q7/22;(IPC1-7):H04B7/26 主分类号 H04B7/26
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