发明名称 MULTIPLE DELAY DETECTION DEMODULATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the C/N by selecting a multiple delay detection section after no error due to effect of an error in the multiple delay detection section is caused so as to reduce occurrence of the error as to a tip of a received signal. SOLUTION: A counter 6 starts counting a symbol clock signal CLK from an identification discrimination section 3 based on a frame signal FS from a TDMA(time division multiplexing access) control section 5 and when a content of the count reaches a setting count, a multiple delay detection section 2 is selected. The changeover is executed by allowing the counter 6 to apply a switching control signal SW to a selector 4. The setting value is selected to be a value corresponding to the multiplexity of the multiple delay detection section 2 or over. After the symbol number corresponding to the multiplexity, discrimination data FD fed back to the multiple delay detection section 2 are all confirmed, and changeover after the discrimination data FD are confirmed allows occurrence of an error and improves the C/N.
申请公布号 JPH09162944(A) 申请公布日期 1997.06.20
申请号 JP19950318790 申请日期 1995.12.07
申请人 FUJITSU LTD 发明人 HATANO TAIJI
分类号 H03D3/02;H04L27/227 主分类号 H03D3/02
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