| 摘要 |
PROBLEM TO BE SOLVED: To more speedily read and write data. SOLUTION: In the ferroelectric memory cell 23a, the drain, gate, and source of an nMIS transistor 30 are connected to a bit wire BL, a word wire WL, and the anode of a ferroelectric diode 10, respectively, and the cathode of the ferroelectric diode 10 is connected to the cell plate of a reference potential Vcom. The ferroelectric diode has an n-type semiconductor/ferroelectric crystal film/metal electrode structure. By symmetrically forming the ferroelectric memory cell for the bit wires BL and *BL, noise margin increases. In other ferroelectric memory cells, the anode and cathode of the ferroelectric diode are connected to the gate and source of the nMIS transistor, respectively, and the drain and source of the nMIS transistor are connected to first and second bit wires, respectively. |
