| 摘要 |
<p>An apparatus for handling bus error signals is providing for a computer having a processor, an interrupt controller, a first PCI bus with first PERR# and SERR# signals, and a second PCI bus with second PERR# and SERR# signals. The apparatus has a buffer with an input connected to ground, an enable input connected to the second SERR# signal, and an output connected to the first SERR# signal. When the second SERR# signal is asserted, the first SERR# signal is also asserted via the buffer and is provided to one input of the interrupt controller. In an alternate embodiment, the buffer enable input is connected to the first SERR# signal and the buffer output connected to the second SERR# signal. The apparatus also receives the first and second PERR# signals and logically ORs the signals together to generate a combine PERR# signal. The combined PERR# signal is presented to a register which is clocked by the PCI system clock to synchronize the combined PERR# signal to a second input of the interrupt controller. The interrupt controller generates an interrupt to the processor and causes the processor to poll devices to identify the board that might have caused the error and to take a corrective action. <IMAGE></p> |
