| 摘要 |
The circuit is for coinciding a synchronism between IOM-2 buses and comprises: a first and a second frame clear signal forming part for respectively forming a frame clear signal having a narrower pulse width than frame synchronism signals of a first and a second IOM-2 bus; a first and a second frequency divider which is cleared upon an appliance of the first and second frame clear signals and receives each data clock signal of the first and second IOM-2 buses and divides the data clock signal into 1/2 frequency and outputs the 1/2 data clock signal; a first and a second half frequency output part which is cleared upon an appliance of the first and second frame clear signals and counts a data clock of the first and second IOM-2 buses and outputs a half frequency corresponding to a half frequency of one frame; a first combination part which logically multiplies the output of the second frequency divider by the output of the second half output part; a first storage part which synchronizes a upward transmission data of the second IOM-2 bus with the output of the first combination part and stores in order and outputs in parallel; a second storage part which is synchronized with the half frequency output signal of the first half frequency output, and inputs and stores the data of the first storage part in parallel, and is synchronized with the 1/2 data clock signal of the first frequency divider so as to output the stored data in order; a third storage part which is synchronized with the output of the first combination part so as to store and output the upward transmission data of the second IOM-2 bus in order.
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