Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states

摘要

An apparatus and method for address pipelining of a computer system that reduce the average number of wait states required to access a dynamic random access memory (DRAM) subsystem. A memory controller addresses a plurality of random access memory integrated circuits in pages of addresses wherein contiguous address pages are in different ones of the plurality of dynamic random access memory integrated circuits. Transparent latches associated with each of the different ones of the plurality of dynamic random access memory integrated circuits allow pipelining of address setups for more than one memory page at substantially the same time. The apparatus and method improve the write access times of a computer system and, when used with a computer system having address pipelining, both read and write accesses are improved because address set up latency time is reduced.