发明名称 |
Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme |
摘要 |
An arbitration circuit which controls arbitration for a resource by a first plurality of agents including a latency sensitive agent. The arbitration circuit comprises a mapping circuit and an arbiter. The mapping circuit is coupled to the first plurality of agents in order to receive a resource request signal from the latency sensitive agent and thereafter produce a plurality of request signals identical to the resource request signal. These request signals are input into at least a first and second I/O ports of the arbiter. The arbiter, which is coupled to the mapping circuit, including a second plurality of I/O ports and a second plurality of control ports each corresponding to one of the I/O ports. The arbiter is configured to arbitrate request signals input into the second plurality of I/O ports including the plurality of request signals, to monitor which I/O port was last activated, and to deactivate a control port associated with the I/O port thereby producing a control signal. This control signal signals the mapping circuit to disable at least one of the plurality of request signals upon detecting that the control signal is associated with the first I/O port or the second I/O port.
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申请公布号 |
US5640519(A) |
申请公布日期 |
1997.06.17 |
申请号 |
US19950528914 |
申请日期 |
1995.09.15 |
申请人 |
INTEL CORPORATION |
发明人 |
LANGENDORF, BRIAN K.;DODD, JAMES M.;HAYEK, GEORGE R. |
分类号 |
G06F13/364;(IPC1-7):G06F13/364;G06F13/36;G06F13/362 |
主分类号 |
G06F13/364 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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