发明名称 |
Single chip network router |
摘要 |
A single chip router for a multiplex communication network comprises a packet memory for storing data packets, a Reduced Instruction Set Computer (RISC) processor for converting the packets between a Local Area Network (LAN) protocol and a Wide Area Network (WAN) protocol, a LAN interface and a WAN interface. A Direct Memory Access (DMA) controller transfers packets transferring packets between the packet memory and the LAN and WAN interfaces. A packet attribute memory stores attributes of the data packets, and an attribute processor performs a non-linear hashing algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet attribute memory. An address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address, and can comprise a dynamic window filter or a static window filter.
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申请公布号 |
US5640399(A) |
申请公布日期 |
1997.06.17 |
申请号 |
US19950529656 |
申请日期 |
1995.09.18 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
ROSTOKER, MICHAEL D.;STELLIGA, D. TONY |
分类号 |
H04L12/46;H04L12/56;H04L12/66;H04L29/06;H04Q11/04;(IPC1-7):H04J3/14 |
主分类号 |
H04L12/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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