发明名称 |
Self-enabling pulse trapping circuit |
摘要 |
An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. An external input is used to terminate and change a burst operation. Circuitry is provided to monitor the external input during burst operations and provide an appropriate control signal.
|
申请公布号 |
US5640364(A) |
申请公布日期 |
1997.06.17 |
申请号 |
US19950568358 |
申请日期 |
1995.12.06 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
MERRITT, TODD;WILLIAMS, BRETT |
分类号 |
G06F12/06;G11C7/10;G11C8/00;G11C11/407;(IPC1-7):G11C8/00 |
主分类号 |
G06F12/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|