| 摘要 |
An apparatus for controlling a D-channel is disclosed. The apparatus comprises a CPU(30) for processing the data provided from an ISDN connector(10) in an HDLC(High Level Data Link Control) mode; a multiplexor/demultiplexor(40) for multiplexing or demultiplexing the data from the ISDN connector(10) and a system hardware; a clock generator, responsive to a synchronizing clock(CLK) and a frame signal(FRAME), for generating a first and a second gating clocks; and a data collision prevention unit(20), responsive to the gating clocks, for controlling the data provided from the CPU and the multiplexor/demultiplexor(40) to prevent the data collision.
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