Semiconductor memory device for use with high density gigabit memory

摘要

The device includes a cell field, two row address buffers, two pre-decoders, and two row decoders. The cell field is provided two cell field blocks whose word lines are selectively controlled by respective row decoders. Also provided is a controller which produces two row address impulse signals in response to an external row address impulse beam signal, a column address impulse beam signal an output activation signal, and a mode activation signal. The two row address buffers produce respective internal row address signals in response to the an external row address signal and respective row address impulse signals. The two pre- decoders transmit pre-decodings of respective internal row address signals to the two row decoders. The address buffers, pre-decoders, and the row decoders are alternately used.