发明名称 Halbleiteranordnung mit Substrat
摘要 A semiconductor device comprising a substrate (3), an optionally thermosetting resin coated or impregnated porous PTFE layer (5) on the substrate separating the substrate from an integrated circuit chip (1). The PTFE layer eliminates thermal and mechanical stress and cracking. <IMAGE>
申请公布号 DE69219509(D1) 申请公布日期 1997.06.12
申请号 DE1992619509 申请日期 1992.03.05
申请人 JAPAN GORE-TEX, INC., TOKIO/TOKYO, JP 发明人 FUKUTAKE, SUNAO, OKAYAMA-SHI, OKAYAMA-KEN 703, JP;HATAKEYAMA, MINORU, AKAIWA-GUN, OKAYAMA-KEN 709-08, JP;HAZAKI, YOSHITO, OKAYAMA-SHI, OKAYAMA-KEN 703, JP;URAKAMI, AKIRA, OKU-GUN, OKAYAMA-KEN 401-42, JP
分类号 H01L21/52;H01L21/48;H01L21/58;H01L23/29;H01L23/31;H01L23/495;H01L29/06 主分类号 H01L21/52
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