| 摘要 |
PURPOSE:To use a reset terminal as a test terminal by measuring the pulse width of a signal inputted to the reset terminal by a fundamental clock and selecting a test mode corresponding to this pulse width. CONSTITUTION:When the pulse width of the signal inputted to a reset terminal 6 is twice as long as the period of a fundamental clock signal N8, the signal applied to the terminal has the waveform shaped and appears as a signal N1. Pulses corresponding to one clock are generated in an output signal N5 of an AND circuit 11 by FFs 8 and 9 and are inputted to a counter 1 through an inverter 12, and 0 is loaded there. The counter 1 is set to the enable state by an output signal N4 of an inverter 10, and the counter 1 can count a maximum of hexadecimal 2 because the inputted signal N8 rises twice during this enable state. Since the enable signal N4 is switched from the high level to the level at this time, the output value of the counter 1 is fixed to 2. Consequently, outputs QA-QD of the counter 1 are fixed to this level, and a decoder 2 outputs a mode signal which selection test mode 2. |
