| 摘要 |
A DC-coupled active pull-down ECL circuit ("LS-APD") has a pull-down drive that self-adjusts to load conditions. A current source sinks emitter current from first and second push-pull transistors. The input signal is coupled to the base of the first transistor, whose inverted collector signal is coupled to the base of a pull-up transistor whose emitter is the LS-APD output voltage node. (A non-inverting configuration provides the input signal to the base of the second transistor.) The pull-up transistor is coupled between the upper rail and the second transistor's collector load resistor. A pull-down transistor has its base coupled to the second transistor's collector, its collector coupled to the LS-APD output node, and its emitter coupled to a node receiving a regulated Vreg voltage. As load capacitance increases, the output voltage takes longer to drop sufficiently to nearly turn-off the pull-down transistor. Thus, the pull-down transistor stays on longer, sinking more current that promotes a more rapid "1" to "0" output voltage transition and providing a self-adjusting drive capability. A voltage regulator that preferably sinks current and is referenced to the upper rail establishes the Vreg reference voltage. The regulator uses a replica of an LS-APD cell to establish and automatically maintain the Vreg level over variations of process deviation, power supply voltage change and temperature change. The voltage regulator circuit establishes a crossover current in each driven LS-APD equal to that present in the replicated cell. |
